1 article was written in May 2012:


Implemementing the frequency counter part 1

So this was long time since the last post. Working with a CPLD for the first time wasn’t trivial, and there are so many other things to do…

I will split this up into two parts, the first showing the frequency counter stuff itself, the second one dealing with connecting it to an MCU and showing the results.

Since I had already drawn a schematic for the simulation, which also worked fine, I decided to implement in the CPLD with a schematic also. I thought that it wasn’t too complex, and wanted to save the effort to learn VHDL or Verilog for later. It turned out to be a mixed success, mainly because the Xilinx schematics editor seems not to be intended to be used for larger projects (though it has some interesting features, it also has some quirks making stuff complicated).

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